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DATA SHEET
MOS INTEGRATED CIRCUIT
PD17P203A, 17P204
4-BIT SINGLE-CHIP MICROCONTROLLER WITH STATIC RAM AND 3-CHANNEL TIMER FOR INFRARED REMOTE CONTROLLER
DESCRIPTION
PD17P203A and PD17P204 are variations of PD17203A and PD17204 respectively and are equipped
with a one-time PROM instead of an internal mask ROM.
PD17P203A and PD17P204 are suitable for evaluating a program when developing PD17203A and PD17204
systems respectively because the program can be written by the user. When reading this document, also refer to the PD17203A and PD17204 Data Sheets.
FEATURES
* 17K architecture: General-purpose register format * Pin-compatible (except for PROM programming function): PD17P203A with PD17203A
PD17P204 with PD17204
* Internal one-time PROM: 4096 x 16 bits (PD17P203A) 7936 x 16 bits (PD17P204) * Static RAM: 16 Kbits (PD17P203A) 8 Kbits (PD17P204) * Power supply voltage: 2.9 to 5.5 V (at TA = -20 to +75C, fX = 4MHz) 2.0 to 5.5 V (at TA = -20 to +75C, fXT = 32kHz) The features of each product is shown in the following table:
Item Pull-up resistor of RESET pin Pull-up resistor of P0A and P0B pins Main clock oscillator circuit Subclock oscillator circuit
PD17P203A-001 PD17P204-001
PD17P203A-002 PD17P204-002 Not provided
Provided Not provided
PD17P203A-003 PD17P204-003
Not provided Provided
PD17203A PD17204
On request (mask option)
Provided
PD17P203A and PD17P204 are different from PD17203A and PD17204 respectively in the power
supply voltage and the operating ambient temperature. Therefore, use PD17P203A and PD17P204 only for the system evaluation.
This document explains PD17P204 as a typical product where no specification is made.
The information in this document is subject to change without notice.
Document No. IC-2851A (O. D. No. IC-8303B) Date Published June 1995 P Printed in Japan
The mark 5 shows major revised points.
(c)
1992
PD17P203A, 17P204
ORDERING INFORMATION
Part Number Package 52-pin plastic QFP (14 x 14 mm) 52-pin plastic QFP (14 x 14 mm) 52-pin plastic QFP (14 x 14 mm) 52-pin plastic QFP (14 x 14 mm) 52-pin plastic QFP (14 x 14 mm) 52-pin plastic QFP (14 x 14 mm)
PD17P203AGC-001-3BH PD17P203AGC-002-3BH PD17P203AGC-003-3BH PD17P204GC-001-3BH PD17P204GC-002-3BH PD17P204GC-003-3BH
2
PD17P203A, 17P204
PIN CONFIGURATION (TOP VIEW)
(1) Normal operation mode
P1B3/TM2OUT P1B2/TM1OUT P1B1/TM0OUT
P1C2/SI
P1C0/SCK
P1C1/SO
LED REM VXRAM VDD XIN XOUT GND0 RESET WDOUT XTIN XTOUT VREG GND5
52 1 2 3 4 5 6 7 8 9 10 11 12 13 14
51
50
49
48
47
46
45
44
43
42
41
40 39 38 37 36 35 34 33 32 31 30 29 28
P0D3
P1C3
P1B0
P1A3
P1A2
P1A1
P1A0
P0D2 P0D1 P0D0 P0C3 P0C2 P0C1 GND4 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3
PD17P203AGC-001-3BH PD17P203AGC-002-3BH PD17P203AGC-003-3BH PD17P204GC-001-3BH PD17P204GC-002-3BH PD17P204GC-003-3BH
15
16
17
18
19
20
21
22
23
24
25
27 26
AMPIN-
CMPIN+
TM0IN
GND1
GND2
VREF
GND3
P0A0
P0A1
AMPOUT
CMPOUT
AMPIN- AMPOUT CMPIN+ CMPOUT INT LED P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P1A0-P1A3 P1B0-P1B3 P1C0-P1C3 REM
: Operational amplifier input : Operational amplifier output : Comparator input : Comparator output : External interrupt input : Remote controller transmission output indicator : I/O port 0A : I/O port 0B : I/O port 0C : I/O port 0D : I/O port 1A : I/O port 1B : I/O port 1C : Remote controller transmission output
RESET SCK SI SO TM0IN TM0OUT TM1OUT TM2OUT VDD VREG VREF VXRAM WDOUT XIN, XOUT XTIN, XTOUT
: Reset input : Serial clock input/output : Serial data input : Serial data output : Timer 0 input : Timer 0 output : Timer 1 output : Timer 2 output : Power supply : Voltage regulator output : Reference voltage output : Static RAM (XRAM) power supply : Overrun detection output : Main clock oscillation use : Subclock oscillation use
GND0-GND5 : Ground
P0A2
INT
3
PD17P203A, 17P204
(2) PROM programming mode
(L)
(Open) GND VDD CLK (Open) GND0 (L) (Open) (L) (Open)
52 1 2 3 4 5 6 7 8 9 10 11 12
51
50
49
48
47
46
45
44
43
42
41
40 39 38 37 36 35 34 33 32 31 30 29 28
D3
D2 D1 D0 D7 D6 D5 GND4 D4 MD3 MD2 MD1 MD0 (L)
PD17P203AGC-001-3BH PD17P203AGC-002-3BH PD17P203AGC-003-3BH PD17P204GC-001-3BH PD17P204GC-002-3BH PD17P204GC-003-3BH
GND5
13 14
15
16
17
18
19
20
21
22
23
24
25
27 26
GND1
(L)
GND2
GND3
(L)
(Open)
(L)
(Open)
VPP
Caution
Those enclosed in parentheses indicate the processing of the pins not used in PROM programming mode. L : Ground these pins through a resistor (470). Open : Do not connect anything to these pins.
CLK D0-D7
: PROM clock input : PROM data I/O
MD0-MD3 VDD VPP
: PROM mode selection : Power supply : Program power supply
GND, GND0-GND5 : Ground
4
(L)
PD17P203A, 17P204
BLOCK DIAGRAM
VREG VDD VXRAM VREF GND0 GND1 GND2 GND3 GND4 GND5
P0A0 P0A1 P0A2 P0A3 P0B0/MD0 P0B1/MD1 P0B2/MD2 P0B3/MD3 P0C0/D4 P0C1/D5 P0C2/D6 P0C3/D7 P0D0/D0 P0D1/D1 P0D2/D2 P0D3/D3 P1A0 P1A1 P1A2 P1A3 P1B0 P1B1/TM0OUT P1B2/TM1OUT P1B3/TM2OUT
Power Supply Circuit P0A
RF P0B RAM 336 x 4 bits P0C SYSTEM REG. TM0IN CMPOUT ALU P0D Remote Control Receiver CMPIN + AMPOUT AMPIN - One Time PROM 4096 x 16 bits (PD17P203A) 7936 x 16 bits (PD17P204)
Instruction Decoder
P1A
P1B
Remote Control Transmitter
REM LED
Timer0/ Counter Timer1/ Counter Timer2/ Counter P1C0/SCK P1C1/SO P1C2/SI P1C3
Program Counter
Stack 5 x 12 bits (PD17P203A) 7 x 13 bits (PD17P204) Interrupt Controller
INT/V PP
P1C XRAM 4096 x 4 bits (PD17P203A) 2048 x 4 bits (PD17P204)
RESET WDOUT
Serial I/O
CPU Clock
Clock Stop XIN/CLK
Main clock XOUT Watch Timer Divider CPU Clock XT IN XT OUT
Subclock
5
PD17P203A, 17P204
CONTENTS 1. PIN FUNCTIONS .....................................................................................................................
1.1 1.2 1.3 NORMAL OPERATION MODE ..................................................................................................... PROM PROGRAMMING MODE ................................................................................................... PIN I/O CIRCUITS ..........................................................................................................................
7
7 9 9
5 5 2.
1.4 1.5
PROCESSING OF UNUSED PINS ................................................................................................ 12 NOTES ON USING RESET AND INT PINS ................................................................................. 13
DIFFERENCES BETWEEN MASK ROM PRODUCTS AND ONE-TIME PROM PRODUCTS .............................................................................................................................. 14 ONE-TIME PROM (PROGRAM MEMORY) WRITING, READING, AND VERIFICATION ............................................................................................................... 15
3.1 3.2 3.3 OPERATION MODE FOR WRITING, READING, AND VERIFICATION OF PROGRAM MEMORY .......................................................................... 15 PROGRAM MEMORY WRITE PROCEDURE ................................................................................ 16 PROGRAM MEMORY READ PROCEDURE ................................................................................. 17
3.
4. 5. 6.
ELECTRICAL SPECIFICATIONS ............................................................................................. 18 PACKAGE DRAWINGS ........................................................................................................... 23 RECOMMENDED SOLDERING CONDITIONS ...................................................................... 24
APPENDIX A. MICROCONTROLLERS FOR LEARNING REMOTE CONTROLLER ............. 25 APPENDIX B. DEVELOPMENT TOOLS ..................................................................................... 26
6
PD17P203A, 17P204
1.
1.1
PIN FUNCTIONS
NORMAL OPERATION MODE
Symbol Function Outputs NRZ signal in synchronization with infrared remote controller signal. Remains low while remote control carrier is output Outputs active-high infrared remote control signal Supplies power to XRAM Positive power Connect 4-MHz ceramic oscillator for main clock oscillation Ground Inputs low-active system reset signal. While this pin remains low level, oscillation of main clock stops. Pull-up resistor can also be connected by mask option (PD17P203A-001 and PD17P204-001 only). Outputs signal for detecting overrun. This pin outputs a low-level when an overflow in the watchdog timer or an overflow/underflow in the stack is detected. Connect this pin to the RESET pin. Connect 32-kHz crystal oscillator across these pins. When option not using subclock is selected, main clock is divided and is supplied to watch timer. Outputs signal from voltage regulator for subclock oscillator circuit. Connect external 0.1-F capacitor. Ground Ground of operation amplifier Inverted input of operational amplifier Ground of operational amplifier Output of operational amplifier Outputs reference voltage of 1/2VDD. Connect external 0.1-F capacitor. Non-inverted input of comparator. Output of this comparator can be obtained from CMPOUT. Ground of operational amplifier Output Format At Reset
(1/2)
Pin No.
1
LED
CMOS push-pull
High-level output
2 3 4 5 6 7
REM VXRAM VDD XIN XOUT GND0
CMOS push-pull - - - -
Low-level output - - (Oscillation stop) -
8
RESET
-
-
9
WDOUT
N-ch open drain
High impedance
5
10 11
XTIN XTOUT
-
(Oscillation)
12
VREG
-
-
13 14 15 16 17 18
GND5 GND1 AMPINGND2 AMPOUT VREF
- - - - - -
- - Input - Output -
19 20
CMPIN+ GND3
- -
Input -
Remark
GND1-GND3 are the ground pins of the operational amplifier. Keep all these pins at the same potential to stabilize the operation of the operational amplifier.
7
PD17P203A, 17P204
(2/2) Pin No. Symbol Function Comparator output. Externally connect CMPOUT and TM0IN when using microcontroller as teaching remote controller Clock input to timer 0. Input clock is sampled by internal clock and then input to envelope signal generator circuit, as well as to timer 0. By using timer 0 with timer 1, frequency of clock input to this pin can be measured. External interrupt signal input pin Constitute 4-bit I/O port, which can be set in input or output mode in 4-bit units. Pull-up resistor can be connected by mask option (PD17P203A-001, -002 and PD17P204-001, -002 only). When one or more of these pins goes low in standby mode standby mode is released. Constitute 4-bit I/O port, which can be set in input or output mode in 4-bit units. Output Format At Reset
21
CMPOUT
-
Output
22
TM0IN
-
Input
23 24 to 27 28 to 31 32 34 to 36 33 37 to 40 41 to 44 45 46 47 48
INT P0A0 to P0A3 P0B0 to P0B3 P0C0 P0C1 to P0C3 GND4 P0D0 to P0D3 P1A0 to P1A3 P1B0 P1B1/ TM0OUT P1B2/ TM1OUT P1B3/ TM2OUT
-
Input
CMOS push-pull
Input
N-ch open drain
Input
Ground Constitute 4-bit I/O port, which can be set in input or output mode in 4-bit units.
-
-
N-ch open drain
Input
Constitute 4-bit I/O port, which can be set in input or output mode in bitwise. Pull-up registor can be connected through program. Port 1B or timer output * P1B0-P1B3 - 4-bit I/O port - Can be set in input/output mode in bitwise - Pull-up resistor can be connected through program * TM0OUT-TM2OUT - Timer output Port 1C or serial interface I/O * P1C0-P1C3 - 4-bit I/O port - Can be set in input/output mode in bitwise * SCK, SO, SI - SCK : serial clock I/O - SO : serial clock data output - SI : serial clock data input
N-ch open drain
Input
N-ch open drain
Input (P1B0-P1B3)
49 50 51 52
P1C0/SCK P1C1/SO P1C2/SI P1C3
CMOS push-pull
Input (P1C0-P1C3)
Caution
For "A" standard products, note that standby mode is released when one or more of P0C and P0D pins goes high in standby mode.
8
PD17P203A, 17P204
1.2 PROM PROGRAMMING MODE
Symbol GND GND0 GND5 GND1 GND2 GND3 GND4 VDD CLK VPP MD0 to MD3 D4 to D7 8-bit data I/O D0 to D3 CMOS push-pull Input Function Output Format At Reset
Pin No. 3 7 13 14 16 20 33 4 5 23 28 to 31 32, 34 to 36 37 to 40
Ground
-
-
Positive power Address updating clock input Supplies program voltage. Apply 12.5V to this pin Selects PROM programming mode
- - - -
- Input - Input
1.3
PIN I/O CIRCUITS
This section shows the I/O circuits of the PD17P204 pins in simplified schematic diagrams. (1) P0A0-P0A3, P0B0/MD0-P0B3/MD3
VDD VDD
Data
Output latch
P-ch
Pull-up resistor Note
Output disable
N-ch
Input buffer
Note
PD17P203A-001, -002 and PD17P204-001, -002 only.
9
PD17P203A, 17P204
(2) P0C0/D4-P0C3/D7, P0D0/D0-P0D3/D3
Data
Output latch
N-ch
Output disable
Input buffer
(3) P1A0-P1A3, P1B0-P1B3/TM2OUT
V DD
Data
Pull-up resistor
P-ch
Data
Output latch
N-ch
Output disable
Input buffer
10
PD17P203A, 17P204
(4) P1C0/SCK-P1C3
V DD
Data
Pull-up resistor VDD
P-ch
Data
Output latch
P-ch
Output disable
N-ch
Input buffer
(5) RESET
V DD
Pull-up resistor Note
Input buffer
Note
PD17P203A-001 and PD17P204-001 only
11
PD17P203A, 17P204
5 1.4 PROCESSING OF UNUSED PINS
The following are recommended to process unused pins.
Table 1-1. Processing of Unused Pins
Pin INT, TM0IN P0A0-P0A3, P0B0-P0B3 Recommended Connection Connect to VDD or GND Input: Connect each pin to VDD through resistor Output: Open (high-level output) Input: Connect each pin to VDD or GND through resistor Output: Open (low-level output) Input: Connect each pin to VDD or GND through resistor Ouput: Open Open Open Connect to GND
P0C0-P0C3, P0D0-P0D3 P1A0-P1A3, P1B0-P1B3 P1C0-P1C3
LED REM WDOUT XIN XOUT XTIN XTOUT AMPIN- AMPOUT, CMPOUT CMPIN+ VREF
Connect to VDD Connect to GND Connect to VREG Connect to GND or AMPOUT Open Connect to GND Open
12
PD17P203A, 17P204
1.5 NOTES ON USING RESET AND INT PINS (NORMAL OPERATION MODE ONLY) 5
In addition to the functions shown in 1. PIN FUNCTIONS, the RESET and INT pins also have a function to set a test mode (for IC testing) in which the internal operations of the PD17P204 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during normal operation, the PD17P204 may be set in the test mode if a noise exceeding VDD is applied. For example, if the wiring length of the RESET or INT pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. * Connect diode with low VF between VDD and RESET/INT pin
VDD
*
Connect capacitor between VDD and RESET/INT pin
VDD
Diode with low VF RESET, INT
VDD
VDD
RESET, INT
13
PD17P203A, 17P204
2. DIFFERENCES BETWEEN MASK ROM PRODUCTS AND ONE-TIME PROM PRODUCTS
The PD17P203A and PD17203 are identical in the CPU functions and internal hardware peripherals except for that the PD17P204 is provided with a PROM, which can be written by the user, in the place of the mask ROM of the PD17204. The only differences between the two microcontrollers are therefore the program memory and mask option. The relation between the PD17P204 and PD17204 is the same as the relation between the PD17P203A and PD17203. Note that the PD17P203A and PD17P204 is slightly different from the PD17203A and PD17204 respectively in electrical characteristics, such as supply voltage and supply current. The following shows the differences between PD17P203A and PD17203A; PD17P204 and PD17204. For the CPU functions and internal hardware peripherals of the PD17203A and PD17P204, therefore, refer to the Data Sheet of the PD17203A and PD17204.
Product Item
PD17P203A-001
PD17P203A-002
* One-time PROM * 0000H-0FFFH * 4096x16 bits Not provided
PD17P203A-003
PD17203A
* Mask ROM * 0000H-0FFFH * 4096x16 bits
Program memory
Pull-up resistor of RESET pin Pull-up resistor of P0A and P0B pins Provided Main clock oscillator circuit Subclock oscillator circuit Vpp pin, PROM program pins Power supply voltage (TA = -20 to 75C) Package
Provided Not provided Provided
Not provided
On request (mask option)
Provided Not provided VDD = 2.2 to 5.5 V (at 4MHz)
VDD = 2.9 to 5.5 V (at 4MHz)Note 52-pin plastic QFP
Product Item
PD17P204-001
PD17P204-002
* One-time PROM * 0000H-1EFFH * 7936x16 bits Not provided
PD17P204-003
PD17204
* Mask ROM * 0000H-1EFFH * 7936x16 bits
Program memory
Pull-up resistor of RESET pin Pull-up resistor of P0A and P0B pins Provided Main clock oscillator circuit Subclock oscillator circuit Vpp pin, PROM program pins Power supply (TA = -20 to 75C) Package
Provided Not provided Provided
Not provided
On request (mask option)
Provided Not provided VDD = 2.2 to 5.5 V (at 4MHz)
VDD = 2.9 to 5.5 V (at 4MHz)Note 52-pin plastic QFP
Note
For details on the power supply voltage, refer to 4. ELECRICAL SPECIFICATIONS.
14
PD17P203A, 17P204
3. ONE-TIME PROM (PROGRAM MEMORY) WRITING, READING, AND VERIFICATION
The program memory of 4096 x 16 bits (PD17P203A) and 7936 x 16 bits (PD17P204) one-time PROM are provided. The following table lists the pins to be used for this PROM writing, reading or verification. In PROM mode, no address input pin is used. Instead, the address is updated by the clock for input from the CLK pin.
Pin Name VPP CLK MD0-MD3 D0-D7
Function Applies program voltage. Inputs address update clock. Selects operation mode. Inputs and outputs 8-bit data.
3.1
OPERATION MODE FOR WRITING, READING, AND VERIFICATION OF PROGRAM MEMORY
If +6 V is applied to the VDD and +12.5 V to the VPP pin after PD17P204 has been placed in the reset status for a fixed time (VDD = 5V, RESET = 0V), PD17P204 enters program memory write, read, or verify mode. The MD0 to MD3 pins are used to set the operation modes listed in the following table. Leave the pins not used for program memory writing, reading, or verification open or ground through pull-down resistors. Operating Mode Specification Operating Mode VPP VDD MD0 H +12.5 V +6 V L L H x: L or H MD1 L H L x MD2 H H H H MD3 L H H H Program memory address 0 clear mode Write mode Read/verify mode Program inhibit mode
15
PD17P203A, 17P204
3.2 PROGRAM MEMORY WRITE PROCEDURE
The program memory write procedure is as follows. High-speed program memory write is possible. (1) Ground the unused pins through pull-down resistors. The CLK pin must be low. (2) Supply 5 V to the VDD pin. The VPP pin must be low. (3) After waiting for 10 microseconds, supply 5 V to the VPP pin. (4) Operate the MD0 to MD3 pins to set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Write data in 1-millisecond write mode. (8) Set program inhibit mode. (9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9). (10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times 1 milliseconds. (11) Set program inhibit mode. (12) Supply a pulse to the CLK pin four times to update the program memory address by 1. (13) Repeat steps (7) to (12) to the last address. (14) Set program memory address 0 clear mode. (15) Change the voltages of VDD and VPP pins to 5 V. (16) Turn off the power supply. Steps (2) to (12) are illustrated below.
X-time repetition Reset Write Verify Additional data write Address increment
VPP VPP VDD GND
VDD+1 VDD VDD GND CLK Hi-Z Data input Hi-Z Hi-Z
Data output
D0-D7
Hi-Z Data input
MD0
MD1
MD2
MD3
16
PD17P203A, 17P204
3.3 PROGRAM MEMORY READ PROCEDURE
(1) Ground the unused pins through pull-down resistors. The CLK pin must be low. (2) Supply 5 V to the VDD pin. The VPP pin must be low. (3) After waiting for 10 microseconds, supply 5 V to the VPP pin. (4) Operate the MD0 to MD3 pins to set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the CLK pin four times. (8) Set program inhibit mode. (9) Set program memory address 0 clear mode. (10) Change the voltages of VDD and VPP pins to 5 V. (11) Turn off the power supply. Steps (2) to (9) are illustrated below.
VPP VPP VDD GND
VDD+1 VDD VDD GND 1 cycle
CLK
D0-D7
Hi-Z
Data output
Data output
Hi-Z
MD0
MD1
"L"
MD2
MD3
17
PD17P203A, 17P204
4. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25C)
Item Supply voltage Input voltage Symbol VDD VI IOH1 IOH2 IOH3 High-level output current IOH4 IOH5 IOH6 IOL1 IOL2 Low-level output current IOL3 IOL4 Operating ambient temperature Storage temperature TA Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 Unit V V mA mA mA mA mA mA mA mA mA mA C C
* * * REM pin * * * * * 1 pin (except for REM pin) * * * * * * Total (except for REM pin) * * * * * * * 1 pin * * * * * * Total * * *
Peak value Effective valueNote
-30 -20 -7.5 -5.0 -22.5 -15.0 7.5 5.0 30 20 -20 to +75 -40 to +125
Peak value Effective valueNote Peak value Effective valueNote
Peak value Effective valueNote Peak value Effective valueNote
Note
Effective value = Peak value x Duty Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product.
Caution
RECOMMENDED OPERATING RANGE (TA = -20 to +75C)
Item Symbol VDD1 VDD2 Supply voltage VDD3 VDD4 Main clock oscillation frequency Subclock oscillation frequency fX fXT Conditions When the system clock is fX = 4 MHz, TA = -20 to 55C When the system clock is fX = 4 MHz When the system clock is fX = 6 MHz, 4.75 TA = -20 to 50C When the system clock is fXT = 32 kHz 2.0 1.0 3.0 4.0 32.768 5.5 8.0 V MHz kHz 5.0 5.5 V 2.7 2.9 3.0 3.0 5.5 5.5 V V MIN. TYP. MAX. Unit
CAPACITANCE (TA = 25C, VDD = 0 V)
Item Input capacitance Symbol CIN CPIN Conditions INT, RESET pins Other than INT, RESET pins MIN. TYP. MAX. 10 10 Unit pF pF
18
PD17P203A, 17P204
DC CHARACTERISTICS (VDD = VXRAM = 3 V, TA = -20 to +75C, fX = 4 MHz, fXT = 32 kHz)
Item High-Level Input Voltage VIH2 VIL1 Low-Level Input Voltage VIL2 IIH1 IIH2 High-Level Input Current IIH3 IIH4 IIH5 IIL1 IIL2 IIL3 RESET IIL4 Low-Level Input Current IIL5 P0A,P0B IIL6 IIL7 IIL8 P1A-P1C IIL9 IOH1 IOH2 High-Level Output Current IOH3 IOH4 IOH5 IOL1 IOL2 IOL3 Low-Level Output Current IOL4 IOL5 IOL6 VREF Output Voltage VREF IDD1 IDD2 Supply Current IDD3 IDD4 IXRAM1 XRAM Supply Current IXRAM2 HALT mode REM Other than RESET, INT pins INT TM0IN RESET VIH = 3 V VIH = 3 V VIH = 3 V 0 0.9 0.2 0.2 0.2 0.2 0.2 -0.2 -0.2 -0.2 -30 -60 -120 -0.2 -8 -15 -30 -0.2 -0.2 -30 -0.6 -0.6 -7.0 -0.3 -0.3 0.5 0.5 1.5 0.5 0.5 0.5 0.8 0.5 -60 -2.0 -2.0 -15.0 -1.0 -1.0 1.5 1.5 4.5 1.5 1.5 1.5 1.1 2.0 400 -120 -4.0 -4.0 -25.0 -2.0 -2.0 2.5 2.5 7.5 2.5 2.5 2.5 1.6 4.0 600 2.0 20 3.0 5.0 0.2 30 7.0 1.0 V Other than RESET, INT pins RESET, INT pins 2.1 0 3.0 0.6 V V Symbol VIH1 Conditions RESET, INT pins MIN. 2.4 TYP. MAX. 3.0 Unit V
A A A A A A A A A A A A A A
mA mA mA mA mA mA mA mA mA mA mA V mA
P0A-P0D VIH = 3 V P1A-P1C VIH = 3 V INT TM0IN VIL = 0 V VIL = 0 V VIL = 0 V, w/o pull-up resistors VIL = 0 V, w/pull-up resistors VIL = 0 V, w/o pull-up resistors VIL = 0 V, w/pull-up resistors P0C,P0D VIL = 0 V VIL = 0 V, w/o pull-up resistors VIL = 0 V, w/pull-up resistors P0A,P0B VOH = 2.7 V P1C REM LED VOH = 2.7 V VOH = 1 V VOH = 2.7 V
CMPOUT VOH = 2.7 V
P0A,P0B,P1C VOL = 0.3 V P0C,P0D,P1B VOL = 0.3 V
P1A
VOL = 0.3 V VOL = 0.3 V
LED,WDOUT VOL = 0.3 V
5
CMPOUT VOL = 0.3 V C = 0.1 F, R = 82 K Generates both XT and X Operation mode Generates XT only Generates both XT and X Generates XT only
A
mA
A A A
Operation mode, VXRAM = 3 V HALT mode, VXRAM = 3 V, TA = 25C
19
PD17P203A, 17P204
XRAM LOW SUPPLY VOLTAGE DATA HOLDING CHARACTERISTICS
(TA = -20 to +75C, VDD VXRAMDR)
Item Data Holding Voltage Symbol VXRAMDR Conditions MIN. 1.3 TYP. MAX. 5.5 Unit V
DC PROGRAMMING CHARACTERISTICS
(TA = 25C, VDD = 6.00.25 V, VPP = 12.50.3 V)
Item High-Level Input Voltage Symbol VIH1 VIH2 Low-Level Input Voltage Input Leakage Current High-Level Output Voltage Low-Level Output Voltage VDD Supply Current VPP Supply Current VIL1 VIL2 ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions Other than CLK CLK Other than CLK CLK VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD -1.0 0.4 30 30 MIN. 0.7 VDD VDD -0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. VPP must not exceed +13.5 V, including the overshoot. 2. Apply VDD before VPP and disconnect it after VPP.
20
PD17P203A, 17P204
AC PROGRAMMING CHARACTERISTICS
(TA = 25C, VDD = 6.00.25 V, VPP = 12.50.3 V)
Item Address Setup TimeNote 2 (vs.MD0) MD1 Setup Time (vs. MD0) Data Setup Time (vs. MD0) Address Hold TimeNote 2 (vs.MD0) Symbol Note 1 tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH,tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR tRES tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR - - - - - - - tACC tOH - -
When data is read from program memory When data is read from program memory When data is read from program memory When data is read from program memory When data is read from program memory
Conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
s s s s s
130 ns
Data Hold Time (vs. MD0) MD0 Data Output Float Delay Time VPP Setup Time (vs. MD3) VDD Setup Time (vs. MD3) Initial Program Pulse Width Additional Program Pulse Width MD0 Setup Time (vs. MD1) MD0 Data Output Delay Time MD1 Hold Time (vs. MD0) MD1 Recovery Time (vs. MD0) Program Counter Reset Time CLK Input High-/Low- Level Width CLK Input Frequency Initial Mode Set Time MD3 Setup Time (vs. MD1) MD3 Hold Time (vs. MD1) MD3 Setup Time (vs. MD0) AddressNote 2 Data Output Delay Time AddressNote 2 Data Output Hold Time
s s
1.0 1.05 21.0 ms ms
s
1
MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125
s s s s s
4.19 2 2 2 2 2 0 2 2 10 130
MHz
s s s s s
ns
MD3 Hold Time (vs. MD0) MD3 Data Output Float Delay Time Reset Setup Time
s s s
Notes
1. These symbols are the corresponding PD27C256 (maintenance product) symbols. 2. The internal address is incremented by 1 at the third falling edge of CLK (with four clocks constituting as one cycle). The internal address is not connected to any pin.
21
PD17P203A, 17P204
PROGRAM MEMORY WRITE TIMING
tRES VPP VDD GND VDD+1 VDD GND CLK D0-D7 Hi-Z t1 MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tM0S tOPW Data input tDS tDH Hi-Z
Data output
tVPS
VPP
tVDS tXH
VDD
Hi-Z Data input tDF tDS
Hi-Z tDH tAH
tXL tAS
Data input
Hi-Z
tDV
PROGRAM MEMORY READ TIMING
tRES tVPS VPP VPP VDD GND VDD+1 VDD GND CLK tXL D0-D7 Hi-Z t1 MD0 tDV tHAD Data output tDAD Data output tM3HR Hi-Z tDFR
tVDS
VDD
tXH
MD1
"L" tPCR
MD2 tM3SR MD3
22
PD17P203A, 17P204
5. PACKAGE DRAWINGS
5
52 PIN PLASTIC QFP (
14)
A B
39 40
27 26
detail of lead end
C
D
S Q
F
52 1
14 13
G
H
I
M
J K
P
N
NOTE
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.20.2 14.00.2 14.00.2 17.20.2 1.0 1.0 0.400.10 0.20 1.0 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.1250.075 55 3.0 MAX. INCHES 0.6770.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.008 0.039 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0050.003 55 0.119 MAX. S52GC-100-3BH-2
Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition.
M
R
23
PD17P203A, 17P204
5
6.
RECOMMENDED SOLDERING CONDITIONS
Soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document "Semiconductor
device mounting technology manual" (IEI-1207). For other soldering methods, please consult with NEC personnel.
Table 6-1. Soldering Conditions of Surface Mount Type
PD17P203AGC-001-3BH : 52-pin plastic QFP (14 x 14 mm) PD17P203AGC-002-3BH : 52-pin plastic QFP (14 x 14 mm) PD17P203AGC-003-3BH : 52-pin plastic QFP (14 x 14 mm) PD17P204GC-001-3BH : 52-pin plastic QFP (14 x 14 mm) PD17P204GC-002-3BH : 52-pin plastic QFP (14 x 14 mm) PD17P204GC-003-3BH : 52-pin plastic QFP (14 x 14 mm)
Soldering Method Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (210C min), Number of times: 2 max., Days: 7 daysNote (after that, prebaking is necessary for 20 hours at 125C) (1) Start second reflow after device temperature (which has risen because of first reflow) has returned to room temperature. (2) Do not clean flux with water after first reflow. Package peak temperature: 215C, Time: 40 seconds max. (200C min), Number of times: 2 max., Days: 7 daysNote (after that, prebaking is necessary for 20 hours at 125C) (1) Start second reflow after device temperature (which has risen because of first reflow) has returned to room temperature. (2) Do not clean flux with water after first reflow. Pin temperature: 300C max., Time: 3 seconds max. (per side of device) Symbol
Infrared reflow
IR35-207-2
VPS
VP15-207-2
Pin part heating
----
Note
The number of days the device can be stored after the dry pack was opened, under storage conditions of 25C and 65% RH max.
Caution
Do not use two or more soldering methods in combination (except the pin partial heating method).
24
PD17P203A, 17P204
APPENDIX A. MICROCONTROLLERS FOR LEARNING REMOTE CONTROLLER
Product Item ROM Capacity RAM Capacity Static RAM Capacity Carrier Generator for Infrared Remote Controller Receiver Preamplifier for Infrared Remote Controller I/O Ports External Interrupt (INT) Timer Watchdog Timer Serial Interface Stack Standby Function Main System Clock Sub-System Clock 4 channels 4096 x 4 bits Provided
PD17203A
4096 x 16 bits (mask ROM)
PD17P203A
4096 x 16 bits (one-time PROM)
PD17204
7936 x 16 bits (mask ROM)
PD17P204
7936 x 16 bits (one-time PROM)
336 x 4 bits 2048 x 4 bits
Provided 28 1 8-bit timer: 3 channels Watch timer: 1 channel
Provided (WDOUT output) 1 channel 5 levels (interrupt nesting: 3 levels) 7 levels (interrupt nesting: 3 levels) STOP and HALT modes 4 s at 4 MHz (VDD = 2.2 to 5.5V) (VDD = 2.9 to 5.5VNote) (VDD = 2.2 to 5.5V) (VDD = 2.9 to 5.5VNote) 488 s at 32.768 kHz (VDD = 2.0 to 5.5 V) 52-pin plastic QFP
Instruction Execution Time (supply voltage) TA = -20 to +75C
Package
Note
The supply voltage varies depending on the operating ambient temperature. For details, refer to 4. ELECTRICAL SPECIFICATIONS.
25
PD17P203A, 17P204
5
APPENDIX B. DEVELOPMENT TOOLS
The following tools are readily available for PD17P203A and PD17P204 program development. Hardware
Name Outline The IE-17K, IE-17K-ET, and EMU-17 are in-circuit emulators that can be commonly used with the 17K series products. The IE-17K and IE-17K-ET are connected to the host machine, which is a PC-9800 series product or IBM PC/ATTM, via RS-232-C. The EMU-17K is inserted into an expansion slot of a PC-9800 series product. When these in-circuit emulators are used in combination with a system evaluation board (SE board) dedicated to each model of the device, they operate as the emulator dedicated to that model. A more sophisticated debugging environment can be created by using the man-machine interface software, SIMPLEHOSTTM. The EMU-17K has a function that allows you to check the contents of the data memory real-time. The SE-17204 is an SE board for the PD17203A, 17P203A, 17204 and 17P204. It may be used alone to evaluated a system, or in combination with an in-circuit emulator for debugging. The EP-17203GC is an emulation probe for the PD17203A, 17P203A, 17204 and 17P204. It connects an SE board and the user system. When used with the EV-9200G-52 this probe connects the SE board and the target system. The EV-9200G-52 connects the EP-17203GC and the target system.
In-circuit emulators IE-17K IE-17K-ETNote 1 EMU-17KNote 2
SE board (SE-17204)
Emulation Probe (EP-17203GC) Conversion socket (EV-9200G-52Note 3) PROM programmer (AF-9703Note 4, AF-9704Note 4 AF-9705Note 4, AF9706Note 4) Program adapter (AF-9808BNote 4)
The AF9703, AF9704, AF9705, and AF9706 are PROM programmers that can program the PD17P203A and 17P204. When connected with programmer adapter AF-9808A, this PROM programmer can program the PD17P203A and 17P204. The AF-9808A is an adapter for programming the PD17P203AGC and 17P204GC and is used in combination with the AF-9703, AF-9704, AF-9705, and AF-9706.
Notes 1. Low-cost model: external power supply type 2. This is a product from I.C., Corp. For details, consult I.C. 3. One EV-9200G-52 is supplied with the EP-17203GC. Five EV-9200G-52s are optionally available as a set. 4. These are products from Ando Electric. For details, consult Ando Electric.
26
PD17P203A, 17P204
Software
Outline Machine AS17K is an assembler that can be used in common with the 17K series products. When developing the program of the PD17P203A and 17P204, AS17K is used in combination with a device file (AS17203, AS17204). AS17203 is a device file for PD17203A, and 17P203A, and it is used in combination with an assembler commonly used for the 17K series (AS17K). AS17204 is a device file for PD17204 and 17P204, and it is used in combination with an assembler for the 17K series (AS17K). SIMPLEHOST is a software package that enables manmachine interface on the WindowsTM when a program is developed by using an incircuit emulator and a personal computer. OS Media
Name
Host
Supply
Order Code
5" 2DH PC-9800 series MS-DOSTM 3.5" 2HD 5" 2HC IBM PC/AT PC DOSTM 3.5" 2HC 5" 2HD PC-9800 series MS-DOS
S5A10AS17K S5A13AS17K S7B10AS17K S7B13AS17K S5A10AS17203
17K series assembler (AS17K)
Device file (AS17203)
3.5" 2HD S5A13AS17203 5" 2HC
S7B10AS17203
IBM PC/AT
PC DOS
3.5" 2HC S7B13AS17203 5" 2HD
PC-9800 series
MS-DOS
S5A10AS17204
Device file (AS17204)
3.5" 2HD S5A13AS17204 5" 2HC
S7B10AS17204
IBM PC/AT
PC DOS
3.5" 2HC S7B13AS17204 5" 2HD
S5A10IE17K S5A13IE17K S7B10IE17K S7B13IE17K
PC-9800 series
MS-DOS 3.5" 2HD Windows 5" 2HC
Support software (SIMPLEHOST)
IBM PC/AT
PC DOS 3.5" 2HC
Remark The corresponding OS versions are as follows:
OS MS-DOS PC DOS Windows Version Ver. 3.30 to Ver. 5.00ANote Ver. 3.1 to Ver. 5.0Note Ver. 3.0 to Ver. 3.1
Note
Ver. 5.00/5.00A of MS-DOS and Ver. 5.0 of PC DOS have a task swap function, but this function cannot be used with this software.
27
PD17P203A, 17P204
[MEMO]
28
PD17P203A, 17P204
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
29
PD17P203A, 17P204
[MEMO]
SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11

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